Popular GitHub Repositories for Verilog

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

CNN acceleration on virtex-7 FPGA with verilog HDL

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Convolutional Neural Network RTL-level Design

Hardware accelerator for convolutional neural networks

Design real-time image processing, object recognition and PID control for Autonomous Drone.

Efficient FPGA-Based Accelerator for Convolutional Neural Networks

[DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers

ES-203 Computer Organization & Architecture CNN on FPGA board

a self-study guide for AI hardware engineers, covering a wide range of topics from foundational knowledge to advanced FPGA and acceleration techniques, Nvidia Jetson and edge AI, and more.

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Code implementation for "A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation" which is to be presented at DAC 2023.

A domain-specific language for bitstream computing

Transformer Bitnet en Verilog